The present invention relates to a clock extracting circuit and a clock extracting method for extracting a clock signal synchronous with input NRZ type serial data from the serial data.
Recently, there has been an increasing demand for high-speed transfer of a large amount of data, and attention has been directed to serial data interfaces that realize a transfer speed of a few hundred Mbps or 1 Gbps or more. In such interface technology, only data that does not include a clock signal component is transmitted, and the data is received on a receiving side by generating a clock signal in synchronism with the input data by a phase-locked loop (PLL) circuit and latching the input data using the generated clock signal.
Such interface technology conventionally uses, for example, a clock extracting device that performs predetermined times oversampling on the basis of a clock signal from a PLL circuit, develops the input data into parallel data, and then extracts a clock signal (see Patent Document 1, for example).
FIG. 6 is a diagram showing an example of a configuration of the conventional clock extracting device.
The clock extracting device shown in FIG. 6 has a sampling circuit 110, data converting units 120, 130, and 140, and a serializer 150. Each block is supplied with a 12-phase clock signal CLK from a PLL circuit not shown in the figure.
A serial NRZ (Non-Return-to-Zero) signal from a transmission line is inputted to the sampling circuit 110. The sampling circuit 110 quantizes each unit of consecutive four pieces of data of the input signal by performing three times oversampling in response to a rising edge of the 12-phase clock signal CLK and thereby generates a first data string developed into parallel data in units of 12 bits.
The data converting unit 120 performs EXOR processing on bits adjacent to each other in the first data string obtained by the sampling circuit 110 and thereby generates a second data string for determining change points in the first data string. The data converting unit 130 refers to a third bit from each change point in the second data string generated by the data converting unit 120 as well as bits preceding and succeeding the third bit and generates a third data string in which when the bits preceding and succeeding the third bit are not change points, the third bit referred to is set as a boundary point, and when the preceding or succeeding bit is a change point, the bit as the change point is set as a boundary point.
The data converting unit 140 generates a clock bit string on the basis of the boundary points in the third data string. Then, the serializer 150 converts the clock bit string from the data converting unit 140 from 12-bit parallel data to 1-bit serial data, whereby a clock signal CLKOUT is extracted.
[Patent Document 1]
Japanese Patent Laid-Open No. 2001-148692 (paragraph numbers [0021] to [0030], FIG. 12)
However, in the case of the clock extracting device that performs data processing after developing serial data into parallel data as described above, the larger a number of bits of parallel data, the larger a scale of hardware. It is therefore difficult to increase an oversampling multiple and enhance the accuracy of clock signal extraction. In addition, with an increase in the speed of data transfer, a PLL circuit is required which can output a multiphase clock having phases shifted more accurately to circuits that process each bit of the parallel data. Thus, when the clock extracting device is applied to a receiving circuit for receiving data transmitted at even an higher speed, especially in the future, circuit scale and power consumption will be increased, and it will not be easy to maintain accuracy.